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altera corporation 745 classic epld family may 1999, ver. 5 data sheet a-ds-classic-05 features n complete device family with logic densities of 300 to 900 usable gates (see table 1 ) n device erasure and reprogramming with non-volatile eprom configuration elements n fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 mhz n 24 to 68 pins available in dual in-line package (dip), plastic j-lead chip carrier (plcc), pin-grid array (pga), and small-outline integrated circuit (soic) packages n programmable security bit for protection of proprietary designs n 100 % generically tested to provide 100 % programming yield n programmable registers providing d, t, jk, and sr flipflops with individual clear and clock controls n software design support featuring the altera ? max+plus ? ii development system on windows-based pcs, as well as sun sparcstation, hp 9000 series 700/800, ibm risc system/6000 workstations, and third-party development systems n programming support with alteras master programming unit (mpu); programming hardware from data i/o, bp microsystems, and other third-party programming vendors n additional design entry and simulation support provided by edif, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and veribest table 1. classic device features feature ep610 ep610i ep910 ep910i ep1810 usable gates 300 450 900 macrocells 16 24 48 maximum user i/o pins 22 38 64 t pd (ns) 10 12 20 f cnt (mhz) 100 76.9 50 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
746 altera corporation classic epld f amil y data sheet general description the altera classic tm device family offers a solution to high-speed, low- power logic integration. fabricated on advanced cmos technology, classic devices also have a turbo-only version, which is described in this data sheet. classic devices support 100 % ttl emulation and can easily integrate multiple pal- and gal-type devices with densities ranging from 300 to 900 usable gates. the classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 mhz. classic devices are available in a wide range of pack ages, including ceramic dual in-line package ( cerdip ) , plastic dual in-line package ( pdip ) , plastic j-lead chip carrier ( plcc ) , ceramic j-lead chip carrier (jlcc), pin-grid array (p ga ) , and small-outline integrated circuit ( soic ) packages . eprom-based classic devices can reduce active power consumption without sacrificing performance. this reduced power consumption makes the classic family well suited for a wide range of low-power applications. c lassic devices are 100 % generically tested devices in windowed packages and can be erased with ultra-violet (uv) light, allowing design changes to be implemented quickly. classic devices use sum-of-products logic and a programmable register. the sum-of-products logic provides a programmable- and /fixed- or structure that can implement logic with up to eight product terms. the programmable register can be individually programmed for d, t, sr, or jk flipflop operation or can be bypassed for combinatorial operation. in addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the and array. alteras proprietary programmable i/o architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. these features make it possible to implement a variety of logic functions simultaneously. classic devices are supported by alteras max+plus ii development system, a single, integrated package that offers schematic, textincluding vhdl, verilog hdl, and the altera hardware description language (ahdl)and waveform design entry , compilation and logic synthesis , simulation and timing analysis , and device programming. the max+plus ii software provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry-standard pc- and workstation- based eda tools. the max+plus ii software runs on windows- based pcs, as well as sun sparcstation, hp 9000 series 700/800, and ibm risc system/6000 workstations. these devices also contain on-boar d logic test cir cuitry to allow veri? cation of function and ac speci? cations during standar d pr oduction ? ow . www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 747 classic epld f amil y data sheet f for more information, see t he max+plus ii programmable logic development system & software data sheet . functional description the classic architecture includes the following elements: n macrocells n programmable registers n output enable/clock select n feedback select macroc ells classic macrocells, shown in figure 1 , can be individually configured for both sequential and combinatorial logic operation. eight product terms form a programmable- and array that feeds an or gate for combinatorial logic implementation. an additional product term is used for asynchronous clear control of the internal register; another product term implements either an output enable or a logic-array-generated clock. inputs to the programmable- and array come from both the true and complement signals of the dedicated inputs , feedbacks from i/o pins that are configured as inputs , and feedbacks from macrocell outputs. signals from dedicated inputs are globally routed and can feed the inputs of all device macrocells. the feedback multiplexer controls the routing of feedback signals from macrocells and from i/o pins. for additional information on feedback select con? gurations, see figur e 3 on page 749 . figure 1. classic device macrocell t o l o g i c a r r a y o u t p u t e n a b l e / c l o c k s e l e c t g l o b a l c l o c k o e c l k p r o g r a m m a b l e r e g i s t e r i n p u t , i / o , a n d m a c r o c e l l f e e d b a c k s l o g i c a r r a y f e e d b a c k s e l e c t c l r q a s y n c h r o n o u s c l e a r v c c www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
748 altera corporation classic epld f amil y data sheet the eight product terms of the programmable- and array feed the 8-input or gate, which then feeds one input to an xor gate. the other input to the xor gate is connected to a programmable bit that allows the array output to be inverted. alteras max+plus ii software uses the xor gate to implement either active-high or active-low logic, or de morgans inversion to reduce the number of product terms needed to implement a function. programmable registers to implement registered functions, each macrocell register can be individually programmed for d, t, jk, or sr operation. if necessary, the register can be bypassed for combinatorial operation. during design compilation, the max+plus ii software selects the most efficient register operation for each registered function to minimize the logic resources needed by the design. registers have an individual asynchronous clear function that is controlled by a dedicated product term. these registers are cleared automatically during power-up. in addition, macrocell registers can be individually clocked by either a global clock or any input or feedback path to the and array. alteras proprietary programmable i/o architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. these features make it possible to simultaneously implement a variety of logic functions. output enable/clock select figure 2 shows the two operating modes (modes 0 and 1) provided by the output enable/clock ( oe / clk ) select. the oe / clk select, which is controlled by a single programmable bit, can be individually configured for each macrocell. in mode 0, the tri-state output buffer is controlled by a single product term. if the output enable is high, the output buffer is enabled. if the output enable is low, the output has a high-impedance value. in mode 0, the macrocell flipflop is clocked by its global clock input signal. in mode 1, the output enable buffer is always enabled, and the macrocell register can be triggered by an array clock signal generated by a product term. this mode allows registers to be individually clocked by any signal on the and array. with both true and complement signals in the and array, the register can be configured to trigger on a rising or falling edge. this product-term-controlled clock configuration also supports gated clock structures. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 749 classic epld f amil y data sheet figure 2. classic output enable/clock se lect fee dback select each macrocell in a classic device provides feedback selection that is controlled by the feedback multiplexer. this feedback selection allows the designer to feed either the macrocell output or the i/o pin input associated with the macrocell back into the and array. the macrocell output can be either the q output of the programmable register or the combinatorial output of the macrocell. different devices have different feedback multiplexer configurations. see figure 3 . figure 3. classic feedback multiplexer con? gurations in mode 0, the register is clocked by the global c lock signal. the o utput is enabled by t he logic from the p roduct term. macrocell output buf fer global clock oe clk and array data output enable/cloc k select oe = product t erm clk = global mode 0 in mode 1, the output is permanently enabled a nd the register is c locked by the product t erm, which allows g ated clocks to be g enerated. oe = enabled clk = product term mode 1 output enable/clock select vcc clr q macrocell output buf fer global clock vcc oe clk and array data clr q q i / o e p 6 1 0 e p 6 1 0 i e p 9 1 0 e p 9 1 0 i e p 1 8 1 0 q i / o e p 1 8 1 0 q i / o g l o b a l q u a d r a n t q u a d r a n t g l o b a l g l o b a l f e e d b a c k m u l t i p l e x e r q u a d r a n t f e e d b a c k m u l t i p l e x e r d u a l f e e d b a c k m u l t i p l e x e r www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
750 altera corporation classic epld f amil y data sheet ep610, ep610i, ep910, and ep910i devices have a global feedback con? guration; either the macr ocell output ( q ) or the i/o pin input ( i/o ) can feed back to the and array so that it is accessible to all other macr ocells. ep1810 macrocells can have either of two feedback configurations: quadrant or dual. most macrocells in ep1810 devices have a quadrant feedback configuration; either the macrocell output or i/o pin input can feed back to other macrocells in the same quadrant. selected macrocells in ep1810 devices have a dual feedback configuration: the output of the macrocell feeds back to other macrocells in the same quadrant, and the i/o pin input feeds back to all macrocells in the device. if the associated i/o pin is not used, the macrocell output can optionally feed all macrocells in the device. in this case, the output of the macrocell passes through the tri-state buffer and uses the feedback path between the buffer and the i/o pin. design s ecurity classic devices contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security because data within c onfiguration elements is invisible. the security bit that controls this function and other program data is reset only when the device is erased. t iming model device timing can be analyzed with the max+plus ii software, with a variety of popular industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 4 . devices have fixed internal delays that allow the user to determine the worst-case timing for any design. the max+plus ii software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for system- level performance evaluation. figure 4. classic t iming model i/o delay t io feedback delay t fd output delay t od t xz t zx input delay t in logic array delay t lad t clr array clock delay t ic register t su t h t ics global clock delay www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 751 classic epld f amil y data sheet timing information can be derived from the timing model and parameters for a particular device. external timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. figure 5 shows the internal timing relationship for internal and external delay parameters. f for more information on device timing, refer to application note 78 (understanding max 5000 & classic timing) in this data book . www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
752 altera corporation classic epld f amil y data sheet figure 5. classic switchi ng w aveforms i / o p i n i n p u t p i n l o g i c a r r a y i n p u t l o g i c a r r a y o u t p u t o u t p u t p i n t i n t l a d t c l r t o d t i o i n p u t m o d e t p d 1 = t i n + t l a d + t o d t p d 2 = t i o + t i n + t l a d + t o d t f d t a s u c l o c k p i n c l o c k i n t o l o g i c a r r a y c l o c k f r o m l o g i c a r r a y d a t a f r o m l o g i c a r r a y r e g i s t e r o u t p u t t o l o g i c a r r a y t r t a c h t i n t f t i c t a c l t a h a r r a y c l o c k m o d e g l o b a l c l o c k p i n g l o b a l c l o c k a t r e g i s t e r d a t a f r o m l o g i c a r r a y t r t i n t i c s t s u t h t f t c h t c l g l o b a l c l o c k m o d e t o d c l o c k f r o m l o g i c a r r a y d a t a f r o m l o g i c a r r a y o u t p u t p i n h i g h - i m p e d a n c e t r i - s t a t e t z x t x z o u t p u t m o d e t r and t f < 3 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low . all timing characteristics are measured at 1.5 v . www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 753 classic epld f amil y data sheet t urbo bit option many classic devices contain a programmable turbo bit tm option to control the automatic power-down feature that enables the low-standby- power mode. when the turbo bit option is turned on, the low-standby- power mode is disabled. all ac values are tested with the turbo bit option turned on. when the device is operating with the turbo bit option turned off (non-turbo mode), a non-turbo adder must be added to the appropriate ac parameter to determine worst-case timing. the non- turbo adder is specified in the ac operating conditions tables for each classic device that supports the turbo mode. generic t e sting classic devices are fully functionally tested. complete testing of each programmable eprom configuration element and all internal logic elements before and after packaging ensures 100 % programming yield. see figure 6 for ac test measurement conditions. these devices also contain on-boar d logic test cir cuitry to allow veri? cation of function and ac speci? cations during standar d pr oduction ? ow . figure 6. ac t est conditions device program ming classic devices can be programmed on 486- and pentium-based pcs with the max+plus ii programmer, an altera logic programmer card, the mpu, and the appropriate device adapter. the mpu performs continuity checking to ensure adequate electrical contact between the adapter and the device. data i/o, bp microsystems, and other programming hardware manufacturers also offer programming support for altera devices. see programming hardware manufacturers f or more information. v c c t o t e s t s y s t e m c 1 ( i n c l u d e s j i g c a p a c i t a n c e ) r 1 8 8 5 w d e v i c e o u t p u t r 2 3 4 0 w power -supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be per formed under ac conditions. large-amplitude, fast ground- current transients normally occur as the device outputs discharge the load capacitances. when these transients ? ow through the parasitic inductance between the device ground pin and the test system ground, signi? cant reductions in obser vable noise immunity can result. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
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altera corporation 755 ep610 epld f e atu res n high-performance, 16-macrocell classic epld C combinatorial speeds with t pd as fast as 10 ns C counter frequencies of up to 100 mhz C pipelined data rates of up to 125 mhz n programmable i/o architecture with up to 20 inputs or 16 outputs and 2 clock pins n ep610 and ep610i devices a re pin-, function-, and programming f ile-compatible n programmable clock option for independent clocking of all registers n macrocells individually programmable as d, t, jk, or sr flipflops, or for combinatorial operation n available in the following packages (see figure 7 ): C 24-pin small-outline integrated circuit (plastic soic only) C 24-pin ceramic and plastic dual in-line package (cerdip and pdip) C 28-pin plastic j-lead chip carrier (plcc) figure 7. ep610 pa ckag e pin-out di agrams package outlines not drawn to scale. windows in ceramic packages only . 28-pin plcc 24-pin soic 24-pin dip i/o input clk1 vcc vcc input i/o i/o i/o i/o i/o i/o i/o nc i/o i/o i/o i/o i/o i/o nc i/o i nput gnd gnd clk2 input i/o 5 6 7 8 9 10 1 1 4 3 2 1 28 27 26 12 13 14 15 16 17 18 25 24 23 22 21 20 19 ep610 ep610i ep610 ep610 ep610i ep610 clk1 input i/o i/o i/o i/o i/o i/o i/o i/o input gnd vcc input i/o i/o i/o i/o i/o i/o i/o i/o input clk2 1 2 3 4 5 6 7 8 9 10 1 1 12 24 23 22 21 20 19 18 17 16 15 14 13 clk1 input i/o i/o i/o i/o i/o i/o i/o i/o input gnd vcc input i/o i/o i/o i/o i/o i/o i/o i/o input clk2 1 2 3 4 5 6 7 8 9 10 1 1 12 24 23 22 21 20 19 18 17 16 15 14 13 ep610 ep610 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
756 altera corporation classic epld f amil y data sheet g eneral description ep610 devices have 16 macrocells, 4 dedicated input pins, 16 i/o pins, and 2 global clock pins (see figure 8 ). each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the i/o input. the clk1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. the clk2 signal is a dedicated global clock input for registers in macrocells 1 through 8. figure 8. ep610 block diagram numbers without parentheses are for dip and soic packages. numbers in parentheses are for j-lead packages. figure 9 shows the typical supply current (i cc ) versus frequency of ep610 devices. figure 9. i cc vs. frequency of ep610 devices ( 2 6 ) ( 2 5 ) ( 2 4 ) ( 2 3 ) ( 2 2 ) ( 2 1 ) ( 2 0 ) ( 1 8 ) 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) ( 1 0 ) ( 1 2 ) 2 ( 3 ) 1 ( 2 ) i n p u t c l k 1 ( 1 3 ) i n p u t 2 3 ( 2 7 ) 1 3 ( 1 6 ) i n p u t c l k 2 3 4 5 6 7 8 9 1 0 1 1 g l o b a l b u s ( 1 7 ) i n p u t 1 4 m a c r o c e l l 9 m a c r o c e l l 1 0 m a c r o c e l l 1 1 m a c r o c e l l 1 2 m a c r o c e l l 1 3 m a c r o c e l l 1 4 m a c r o c e l l 1 5 m a c r o c e l l 1 6 m a c r o c e l l 1 m a c r o c e l l 2 m a c r o c e l l 3 m a c r o c e l l 4 m a c r o c e l l 5 m a c r o c e l l 6 m a c r o c e l l 7 m a c r o c e l l 8 f r e q u e n c y 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 8 0 m h z 0 . 1 1 . 0 1 0 0 1 0 t u r b o n o n - t u r b o v c c = 5 . 0 v t a = 2 5 c t y p i c a l i a c t i v e ( m a ) c c www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 757 classic epld f amil y data sheet figur e 10 shows the typical output drive characteristics of ep610 devices. figure 10. output drive characteristics of ep610 devices e p 6 1 0 - 1 5 & e p 6 1 0 - 2 0 e p l d s e p 6 1 0 - 2 5 , e p 6 1 0 - 3 0 & e p 6 1 0 - 3 5 e p l d s v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 i o l i o h 8 0 6 0 4 0 2 0 0 . 4 5 v c c = 5 . 0 v t a = 2 5 c v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 i o l i o h 2 0 0 1 5 0 1 0 0 5 0 0 . 4 5 v c c = 5 . 0 v t a = 2 5 c e p 6 1 0 i e p l d s v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 1 0 0 8 0 6 0 4 0 2 0 i o l i o h v c c = 5 . 0 v t a = 2 5 c t y p i c a l i o u t p u t c u r r e n t ( m a ) c c t y p i c a l i o u t p u t c u r r e n t ( m a ) c c t y p i c a l i o u t p u t c u r r e n t ( m a ) c c drive characteristics may exceed shown cur ves. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
758 altera corporation classic epld f amil y data sheet operating conditions tables 2 through 7 p rovide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for ep610 and ep610i devices . table 2. ep610 & ep610i device absolute maximum ratings notes (1) , (2) symbol parameter conditions ep610 ep610i unit min max min max v cc supply voltage with respect to groun d (3) C2.0 7.0 C2.0 7.0 v v i dc input voltage C2.0 7.0 C0.5 v cc + 0.5 v i max dc v cc or ground current C175 175 ma i out dc output current, per pin C25 25 ma t stg storage temperature no bias C65 150 C65 150 c t amb ambient temperature under bias C65 135 C 65 135 c t j junction temperature ceramic packages, under bias 150 150 c plastic packages, under bias 135 135 c table 3. ep610 & ep610i device recommended operating conditions note (2) symbol parameter conditions ep610 ep610i unit min max min max v cc supply voltage (4) 4.75 (4.5) 5.25 (5.5) 4.75 5.25 v v i input voltage C 0 .3 v cc + 0.3 C 0 .3 v cc + 0.3 v v o output voltage 0 v cc 0 v cc v t a operating temperature for commercial use 0 70 0 70 c for industrial use C40 85 C40 85 c t r input rise time (5) 100 (50) 500 ns t f input fall time (5) 100 (50) 500 ns table 4. ep610 & ep610i device dc operating conditions note (6) symbol parameter conditions min max unit v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage C0.3 0.8 v v oh high-level ttl output voltage i oh = C4 ma dc (7) 2.4 v high-level cmos output voltage i oh = C0.6 ma dc (7) , (8) 3.84 v v ol low-level output voltage i ol = 4 ma dc (7) 0.45 v i i i/o pin leakage current of dedicated input pins v i = v cc or ground C10 10 a i oz tri-state output leakage current v o = v cc or ground C10 10 a www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 759 classic epld f ami l y data sheet table 5. ep610 & ep610i device capacitance note (9) symbol parameter conditions ep610 -15 ep610-20 ep610-25 ep610-30 ep610-35 ep610i unit min max min max min max c in input pin capacitance v in = 0 v, f = 1.0 mhz 10 20 8 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 12 20 8 pf c clk1 clk1 pin capacitance v in = 0 v, f = 1.0 mhz 20 20 10 pf c clk2 clk2 pin capacitance v in = 0 v, f = 1.0 mhz 20 50 12 pf table 6. ep610 device i cc supply current notes ( 2 ) , (10) symbol parameter conditions speed grade ep610 unit min typ max i cc1 v cc supply current (non-turbo, standby) v i = v cc or ground, no load (11) , (12) 20 150 a i cc2 v cc supply current (non-turbo, active) v i = v cc or ground, no load, f = 1.0 mhz (11) , (12) 5 10 (15) ma i cc3 v cc supply current (turbo, active) v i = v cc or ground, no load, f = 1.0 mhz (12) -15, -20 60 90 (115) ma -25, -30, -35 45 60 (75) ma table 7. ep610i device i cc supply current note ( 10 ) symbol parameter conditions ep610i unit min typ max i cc1 v cc supply current (non-turbo, standby) v i = v cc or ground, no load, (11) , (12) 20 150 a i cc2 v cc supply current (non-turbo, active) v i = v cc or ground, no load, f = 1.0 mhz (11) , (12) 3 8 ma i cc3 v cc supply current (turbo, active) v i = v cc or ground, no load, f = 1.0 mhz (12) 65 105 ma www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
760 altera corporation classic epld f amil y data sheet n otes to tables: (1) see the operating requirements for altera devices data sheet in this data book. (2) numbers in parentheses are for industrial-temperature-range devices. (3) the minimum dc input is C0.3 v. during transitions, the inputs may undershoot to C2.0 v (ep610) or C0.5 v (ep610i) or overshoot to 7.0 v (ep610) or v cc + 0.5 v (ep610i) for input currents less than 100 ma and periods less than 20 ns. (4) for ep610 devices, maximum v cc rise time is 50 ms. for ep610i devices, maximum v cc rise time is unlimited with monotonic rise. (5) for ep610-15 and ep610-20 devices: t r and t f = 40 ns. for ep610-15 and ep610-20 clocks: t r and t f = 20 ns. (6) t hese values are specified in table 3 on page 758 . (7) t he i oh parameter refers to high-level ttl or cmos output current; the i ol parameter refers to low-level ttl output current. (8) this parameter does not apply to ep610i devices. (9) the device capacitance is measured at 25 c and is sample-tested only. (10) typical values are for t a = 25 c and v cc = 5 v. (11) when the turbo bit option is not set (non-turbo mode), ep610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. when the turbo bit option is not set, ep610i devices enter standby mode if no logic transitions occur for 75 ns after the last transition. (12) measured with a device programmed as a 16-bit counter. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 761 classic epld f amil y data sheet tables 8 and 9 show the timing parameters for ep610-15 and ep610-20 devices. table 8. ep610-15 & ep610-20 external timing parameters notes ( 1 ), ( 2 ) symbol parameter conditions ep610-15 ep610-20 non-turbo adder unit min max min max (3) t pd1 input to non-registered output c1 = 35 pf 15 .0 20 .0 20 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 17 .0 22 .0 20 .0 ns t pzx input to output enable c1 = 35 pf 15 .0 20 .0 20 .0 ns t pxz input to output disable c1 = 5 pf (4) 15 .0 20 .0 20 .0 ns t clr asynchronous output clear time c1 = 35 pf 15 .0 20 .0 20 .0 ns f max maximum clock frequency (5) 83.3 62.5 0 .0 mhz t su global clock input setup time 9 .0 11 .0 20 .0 ns t h global clock input hold time 0 .0 0 .0 0 .0 ns t ch global clock high time 6 .0 8 .0 0 .0 ns t cl global clock low time 6 .0 8 .0 0 .0 ns t co1 global clock to output delay 11 .0 13 .0 0 .0 ns t cnt global clock minimum period 12 .0 16 .0 0 .0 ns f cnt maximum internal global clock frequency (6) 83.3 62.5 0 .0 mhz t asu array clock input setup time 6 .0 8 .0 20 .0 ns t ah array clock input hold time 6 .0 8 .0 0 .0 ns t ach array clock high time 7 .0 9 .0 0 .0 ns t acl array clock low time 7 .0 9 .0 0 .0 ns t odh output data hold time after clock c1 = 35 pf (7) 1 .0 1 .0 1 .0 ns t aco1 array clock to output delay 15 .0 2 0.0 20 .0 ns t acnt array clock minimum period 14 .0 18 .0 0 .0 ns f acnt array clock internal maximum frequency (6) 71.4 55.6 0 .0 mhz table 9. ep610-15 & ep610-20 int ernal timing parameters (part 1 of 2) symbol parameter conditions ep610-15 ep610-20 unit min max min max t in input pad and buffer delay 4 .0 4 .0 ns t io i/o input pad and buffer delay 2 .0 2 .0 ns t lad logic array delay 6 .0 11 .0 ns t od output buffer and pad delay c1 = 35 pf 5 .0 5 .0 ns t zx output buffer enable delay c1 = 35 pf 5 .0 5 .0 ns t xz output buffer disable delay c1 = 5 pf 5 .0 5 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
762 altera corporation classic epld f amil y data sheet tables 10 and 11 show the timing parameters for ep610-25, ep610-30 and ep610-35 devices. t su register setup time 5 .0 4 .0 ns t h register hold time 4 .0 7 .0 ns t ic array clock delay 6 .0 11 .0 ns t ics global clock delay 2 .0 4 .0 ns t fd feedback delay 1 .0 1 .0 ns t clr register clear time 6 .0 11 .0 ns table 9. ep610-15 & ep610-20 int ernal timing parameters (part 2 of 2) symbol parameter conditions ep610-15 ep610-20 unit min max min max table 10. ep610-25, ep610-30 & ep610-35 external timing parameters notes (1) , ( 2 ) symbol parameter conditions ep610-25 ep610-30 ep610-35 non-turbo adder unit min max min max min max (3) t pd1 input to non-registered output c1 = 35 pf 25 .0 30 .0 35 .0 30 .0 ns t pd2 i/o input to non-registered output 27 .0 32 .0 37 .0 30 .0 ns t pzx input to output enable 25 .0 30 .0 35 .0 30 .0 ns t pxz input to output disable c1 = 5 p f ( 4 ) 25 .0 30 .0 35 .0 30 .0 ns t clr asynchronous output clear time c1 = 35 pf 27 .0 32 .0 37 .0 30 .0 ns f max maximum frequency (5) 47.6 41.7 37 .0 0 .0 mhz t su global clock input setup time 21 .0 24 .0 27 .0 30 .0 ns t h global clock input hold time 0 .0 0 .0 0 .0 0 .0 ns t ch global clock high time 10 .0 11 .0 12 .0 0 .0 ns t cl global clock low time 10 .0 11 .0 12 .0 0 .0 ns t co1 global clock to output delay 15 .0 17 .0 20 .0 0 .0 ns t cnt global clock minimum period 25 .0 30 .0 35 .0 0 .0 ns f cnt max imum i nternal global clock frequency (6) 40 .0 33.3 28.6 0 .0 mhz t asu array clock input setup time 8 .0 8 .0 8 .0 30 .0 ns t ah array clock input hold time 12 .0 12 .0 12 .0 0 .0 ns t ach array clock high time 10 .0 11 .0 12 .0 0 .0 ns t acl array clock low time 10 .0 11 .0 12 .0 0 .0 ns t odh output data hold time after clock c1 = 35 p f (7) 1 .0 1 .0 1 .0 ns t aco1 array clock to output delay 27 .0 32 .0 37 .0 30 .0 ns t acnt array clock minimum period 25 .0 30 .0 35 .0 0 .0 ns f acnt max imum i nternal global clock frequency (6) 40 .0 33.3 28.6 0 .0 mhz www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 763 classic epld f amil y data sheet notes to tables: (1) these values are specified in table 3 on page 758 . (2) see application note 78 (understanding max 5000 & classic timing) in this data book for information on internal timing parameters. (3) the non-turbo adder must be added to this parameter when the turbo bit option is off. (4) sample-tested only for an output change of 500 mv. (5) the f max values represent the highest frequency for pipelined data. (6) measured with a device programmed as a 16-bit counter. (7) sample-tested only. this parameter is a guideline based on extensive device characterization. this parameter applies for both global and array clocking. table 11. ep610-25, ep610-30 & ep610-35 internal timing parameters symbol parameter condition ep610-25 ep610-30 ep610-35 unit min max min max min max t in input pad and buffer delay 8 .0 9 .0 11 .0 ns t io i/o input pad and buffer delay 2 .0 2 .0 2 .0 ns t lad logic array delay 11 .0 14 .0 15 .0 ns t od output buffer and pad delay c1 = 35 pf 6 .0 7 .0 9 .0 ns t zx output buffer enable delay c1 = 35 pf 6 .0 7 .0 9 .0 ns t xz output buffer disable delay c1 = 5 pf 6 .0 7 .0 9 .0 ns t su register setup time 11 .0 11 .0 12 .0 ns t h register hold time 10 .0 10 .0 10 .0 ns t ic array clock delay 13 .0 16 .0 17 .0 ns t ics global clock delay 1 .0 1 .0 0 .0 ns t fd feedback delay 3 .0 5 .0 8 .0 ns t clr register clear time 13 .0 16 .0 17 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
764 altera corporation classic epld f amil y data sheet tables 12 and 13 show the timing parameters for ep610i devices. table 12. ep610i ext ernal timing parameters notes (1) , ( 2 ) symbol parameter conditions ep610i-10 ep610i-12 ep610i-15 non-turbo adder unit min max min max min max (3) t pd1 input to non-registered output c1 = 35 pf 10 .0 12 .0 15 .0 25 .0 ns t pd2 i/o input to non-registered output 10 .0 12 .0 15 .0 25 .0 ns t pzx input to output enable 15 .0 15 .0 18 .0 25 .0 ns t pxz input to output disable c1 = 5 p f (4) 13 .0 15 .0 18 .0 25 .0 ns t clr asynchronous output clear time c1 = 35 pf 13 .0 15 .0 18 .0 25 .0 ns f max maximum frequency (5) 125 .0 100 . 0 83.3 0 .0 mhz t su global clock input setup time 7 .0 9 .0 12 .0 25 ns t h global clock input hold time 0 .0 0 .0 0 .0 0 .0 ns t ch global clock high time 5 .0 5 .0 5 .0 0 .0 ns t cl global clock low time 5 .0 5 .0 5 .0 0 .0 ns t co1 global clock to output delay 6.5 8 .0 8 .0 0 .0 ns t cnt global clock minimum period 10 .0 12 .0 15 .0 25 .0 ns f cnt maximum internal global clock frequency (6) 100 .0 83.3 66 .0 0 .0 mhz t asu array clock input setup time 1.5 3 .0 4 .0 25 .0 ns t ah array clock input hold time 5.5 6 .0 6 .0 0 .0 ns t ach array clock high time 5 .0 5 .0 6 .0 0 .0 ns t acl array clock low time 5 .0 5 .0 6 .0 0 .0 ns t odh output data hold time after clock c1 = 35 pf (7) 1.0 1.0 1.0 ns t aco1 array clock to output delay 12 .0 14 .0 16 .0 25 .0 ns t acnt array clock minimum period 10 .0 12 .0 15 .0 25 .0 ns f acnt maximum internal array clock frequency (6) 100 .0 83.3 66 .0 0 .0 mhz www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 765 classic epld f amil y data sheet notes to tables: (1) these values are specified in table 3 on page 758 . (2) see application note 78 (understanding max 5000 & classic timing) in th is data book f or more information on classic timing parameters. (3) the non-turbo adder must be added to this parameter when the turbo bit option is off. (4) sample-tested only for an output change of 500 mv. (5) the f max values represent the highest frequency for pipelined data. (6) measured with a device programmed as a 16-bit counter. (7) sample-tested only. this parameter is a guideline based on extensive device characterization. this parameter applies for both global and array clocking. table 13. ep610 internal timing parameters symbol parameter conditions ep610i-10 ep610i-12 ep610i-15 unit min max min max min max t in input pad and buffer delay 1.5 4 .0 4 .0 ns t io i/o input pad and buffer delay 0 .0 0 .0 0 .0 ns t lad logic array delay 5.5 6 .0 9 .0 ns t od output buffer and pad delay c1 = 35 pf 3 .0 2 .0 2 .0 ns t zx output buffer enable delay c1 = 35 pf 8 .0 5 .0 6 .0 ns t xz output buffer disable delay c1 = 5 pf 6 .0 5 .0 6 .0 ns t su register setup time 3.5 5 .0 5 .0 ns t h register hold time 3.5 4 .0 7 .0 ns t ic array clock delay 7.5 8 .0 10 .0 ns t ics global clock delay 2 .0 2 .0 2 .0 ns t fd feedback delay 1 .0 1 .0 1 .0 ns t clr register clear time 8.5 9 .0 12 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
notes: www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 767 ep910 epld f e at ures n high-performance, 24-macrocell classic epld C combinatorial speeds with t pd as fast as 12 ns C counter frequencies of up to 76.9 mhz C pipelined data rates of up to 125 mhz n programmable i/o architecture with up to 36 inputs or 24 outputs n ep910 and ep910i devices a re pin-, function-, and programming file- compatible n programmable clock option for independent clocking of all registers n macrocells individually programmable as d, t, jk, or sr flipflops, or for combinatorial operation n available in the following packages (see figure 11 ) C 44-pin plastic j-lead chip carrier (plcc) C 40-pin ceramic and plastic dual in-line packages (cerdip and pdip) figure 11. ep910 pac kag e p in-o ut diagrams package outlines are not drawn to scale. windows in ceramic packages only . 40-pin dip 44-pin plcc ep910 ep910i ep910 ep910i i/o input input input clk1 vcc vcc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o nc nc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input gnd gnd clk2 input input input i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 1 1 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 clk1 input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input gnd vcc input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input clk2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
768 altera corporation classic epld f amil y data sheet general description altera ep910 devices can implement up to 450 usable gates of s si a nd m si l ogic functions. ep910 devices have 24 macrocells, 12 dedicated input pins, 24 i/o pins, and 2 global clock pins (see figure 12 ). each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the i/o input. the clk1 and clk2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively. figure 12. ep910 block diagram numbers without parentheses are for dip packages. numbers in parentheses are for j-lead packages. (40) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) 36 35 34 33 32 31 30 29 28 27 26 25 (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (18) m acrocell 13 macrocell 14 macrocell 15 macrocell 16 macrocell 17 macrocell 18 macrocell 19 macrocell 20 macrocell 21 macrocell 22 macrocell 23 macrocell 24 macrocell 1 macrocell 2 macrocell 3 macrocell 4 macrocell 5 macrocell 6 macrocell 7 macrocell 8 macrocell 9 macrocell 10 macrocell 1 1 macrocell 12 2 (3) 3 (4) 4 (5) 1 (2) input input input clk1 (19) (20) (21) input input input 39 38 37 21 input input input clk2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 global bus (27) (26) (25) input input input 24 23 22 (43) (42) (41) (24) www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 769 classic epld f amil y data sheet figure 13 shows the typical supply current (i cc ) versus frequency of ep910 devices. figure 13. i cc vs. frequency of ep910 devices figur e 14 shows the typical output drive characteristics of ep910 devices. figure 14. output drive characteristics of ep910 devices 1 k h z 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 4 0 m h z f r e q u e n c y v = 5 . 0 v t = 2 5 c t y p i c a l i a c t i v e ( m a ) c c n o n - t u r b o t u r b o 1 0 0 1 0 1 . 0 0 . 1 c c a drive characteristics may exceed shown cur ves. v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 6 0 5 0 4 0 3 0 2 0 1 0 0 0 . 4 5 i o l i o h v c c = 5 . 0 v t a = 2 5 c e p 9 1 0 e p l d s v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 1 2 0 1 0 0 8 0 6 0 4 0 2 0 0 . 4 5 e p 9 1 0 i e p l d s i o l i o h v c c = 5 . 0 v t a = 2 5 c t y p i c a l i o u t p u t c u r r e n t ( m a ) o t y p i c a l i o u t p u t c u r r e n t ( m a ) o www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
770 altera corporation classic epld f amil y data sheet operating conditions tables 14 through 18 p rovide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for ep910 and ep910i devices . table 14. ep910 & ep910i device absolute maximum ratings notes (1) , (2) symbol parameter conditions ep910 ep910i unit min max min max v cc supply voltage with respect to ground (3) C2.0 7.0 C2.0 7.0 v v i dc input voltage C2.0 7.0 C0.5 v cc + 0.5 v i max dc v cc or ground current C250 250 ma i out dc output current, per pin C25 25 ma t stg storage temperature no bias C65 150 C65 150 c t amb ambient temperature under bias C65 135 C 65 135 c t j junction temperature ceramic packages, under bias 150 150 c plastic packages, under bias 135 135 c table 15. ep910 & ep910i device recommended operating conditions note (2) symbol parameter conditions ep910 ep910i unit min max min max v cc supply voltage (4) 4.75 (4.5) 5.25 (5.5) 4.75 5.25 v v i input voltage C 0 .3 v cc + 0.3 C 0 .3 v cc + 0.3 v v o output voltage 0 v cc 0 v cc v t a operating temperature for commercial use 0 70 0 70 c for industrial use C40 85 c t r input rise time (5) 100 (50) 500 ns t f input fall time (5) 100 (50) 500 ns table 16. ep910 & ep910i device dc operating conditions notes ( 6 ), ( 7 ) symbol parameter conditions min max unit v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage C0.3 0.8 v v oh high-level ttl output voltage i oh = C4 ma dc (8) 2.4 v high-level cmos output voltage i oh = C 0.6 ma dc (8) , (9) 3.84 v v ol low-level output voltage i ol = 4 ma dc (8) 0.45 v i i i/o leakage current of dedicated input pins v i = v cc or ground C10 10 a i oz tri-state output leakage current v o = v cc or ground C10 10 a www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 771 classic epld f amil y data sheet n otes to tables: (1) see the operating requirements for altera devices data sheet in this data book. (2) numbers in parentheses are for industrial-temperature-range devices. (3) the minimum dc input is C0.3 v. during transitions, the inputs may undershoot to C2.0 v (ep910) or C0.5 v (ep910i) or overshoot to 7.0 v (ep910) or v cc + 0.5 v (ep910i) for input currents less than 100 ma and periods less than 20 ns. (4) m aximum v cc rise time for ep910 devices = 50 ms; for ep910i devices, maximum v cc rise time is unlimited with monotonic rise. (5) for all clocks: t r and t f = 100 ns (50 ns for the industrial-temperature-range version). (6) these values are specified in table 15 on page 770 . (7) the device capacitance is measured at 2 5 c and is sample-tested only. (8) the i oh parameter refers to high-level ttl or cmos output current; the i ol parameter refers to low-level ttl output current. (9) this parameter does not apply to ep910i devices. (10) w hen the turbo bit option is not set (non-turbo mode), an ep910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an ep910i device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (11) measured with a device programmed as a 24-bit counter. table 17. ep910 & ep910i device capacitance note (6) symbol parameter conditions ep910 ep910i unit min max min max c in input pin capacitance v in = 0 v, f = 1.0 mhz 20 8 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 20 8 pf c clk1 clk1 pin capacitance v in = 0 v, f = 1.0 mhz 20 10 pf c clk2 clk2 pin capacitance v in = 0 v, f = 1.0 mhz 60 12 pf table 18. ep910 & ep910i device i cc supply current notes (2) , (6) , (7) symbol parameter conditions ep910 ep910i unit min typ max min typ max i cc1 v cc supply current (non-turbo, standby) v i = v cc or ground, no load (10) , (11) 20 150 60 150 a i cc2 v cc supply current (non-turbo, active) v i = v cc or ground, no load, f = 1.0 mhz (10) , (11) 6 20 4 12 ma i cc3 v cc supply current (turbo, active) v i = v cc or ground, no load, f = 1.0 mhz (11) 45 80 (100) 120 150 ma www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
772 altera corporation classic epld f amil y data sheet tables 19 and 20 sho w the timing parameters for ep910 devices. table 19. ep910 external timing parameters notes ( 1 ), (2) symbol parameter conditions ep910-30 ep910-35 ep910-40 non- turbo adder ( 3 ) unit min max min max min max t pd1 input to non-registered output c1 = 35 pf 30 .0 35 .0 40 .0 30 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 33 .0 38 .0 43 .0 30 .0 ns t pzx input to output enable c1 = 35 pf 30 .0 35 .0 40 .0 30 .0 ns t pxz input to output disable c1 = 5 p f ( 4 ) 30 .0 35 .0 40 .0 30 .0 ns t clr asynchronous output clear time c1 = 35 pf 33 .0 38 .0 43 .0 30 .0 ns f max maximum frequency ( 5 ) 41.7 37 .0 32.3 0 .0 mhz t su global clock input setup time 24 .0 27 .0 31 .0 30 .0 ns t h global clock input hold time 0 .0 0 .0 0 .0 0 .0 ns t ch global clock high time 12 .0 13 .0 15 .0 0 .0 ns t cl global clock low time 12 .0 13 .0 15 .0 0 .0 ns t co1 global clock to output delay c1 = 35 pf 18 21 .0 24 .0 0 .0 ns t cnt global clock minimum clock period ( 6 ) 30 .0 35 .0 40 .0 0 .0 ns f cnt maximum internal global clock frequency ( 6 ) 33.3 28.6 25 .0 0 .0 mhz t asu array clock input setup time 10 .0 10 .0 10 .0 30 .0 ns t ah array clock input hold time 15 .0 15 .0 15 .0 0 .0 ns t ach array clock high time 15 .0 16 .0 17 .0 0 .0 ns t acl array clock low time 15 .0 16 .0 17 .0 0 .0 ns t odh output data hold time after clock c1 = 35 pf (7) 1.0 1.0 1.0 ns t aco1 array clock to output delay c1 = 35 pf 33 .0 38 .0 43 .0 30 .0 ns t acnt array clock minimum clock period 30 .0 35 .0 40 .0 0 .0 ns f acnt max imum i nternal array clock frequency (6) 33.3 28.6 25 .0 0 .0 mhz www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 773 classic epld f amil y data sheet notes to tables: (1) these values are specified in table 15 on page 770 . (2) see application note 78 (understanding max 5000 & classic timing) in this data book for more information on classic timing parameters. (3) the non-turbo adder must be added to this parameter when the turbo bit option is off. (4) sample-tested only for an output change of 500 mv. (5) the f max values represent the highest frequency for pipelined data. (6) measured with a device programmed as a 24-bit counter. (7) sample-tested only. this parameter is a guideline based on extensive device characterization and applies for both global and array clocking. table 20. ep910 interna l timing parameters symbol parameter condition ep910-30 ep910-35 ep910-40 unit min max min max min max t in input pad and buffer delay 9 .0 10 .0 13 .0 ns t io i/o input pad and buffer delay 3 .0 3 .0 3 .0 ns t lad logic array delay 14 .0 16 .0 17 .0 ns t od output buffer and pad delay c1 = 35 pf 7 .0 9 .0 10 .0 ns t zx output buffer enable delay c1 = 35 pf 7 .0 9 .0 10 .0 ns t xz output buffer disable delay c1 = 5 pf 7 .0 9 .0 10 .0 ns t su register setup time 12 .0 13 .0 15 .0 ns t h register hold time 12 .0 12 .0 12 .0 ns t ic array clock delay 17 .0 19 .0 20 .0 ns t ics global clock delay 2 .0 2 .0 1 .0 ns t fd feedback delay 4 .0 6 .0 8 .0 ns t clr register clear time 17 .0 19 .0 20 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
774 altera corporation classic epld f amil y data sheet tables 21 and 22 show the timing parameters for ep910i devices. table 21. ep910i external timing parameters notes (1) , (2) symbol parameter conditions ep910i-12 ep910i-15 ep910i-25 non-turbo adder unit min max min max min max (3) t pd1 input to non-registered output c1 = 35 pf 12 .0 15 .0 25 .0 40 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 12 .0 15 .0 25 .0 40 .0 ns t pzx input to output enable c1 = 35 pf 15 .0 18 .0 28 .0 40 .0 ns t pxz input to output disable c1 = 35 pf (4) 15 .0 18 .0 28 .0 40 .0 ns t clr asynchronous output clear time c1 = 35 pf 15 .0 18 .0 28 .0 40 .0 ns f max global clock maximum frequency (5) 125 .0 100 .0 62.5 0 .0 mhz t su global clock input setup time 8 .0 11 .0 16 .0 40 .0 ns t h global clock input hold time 0 .0 0 .0 0 .0 0 .0 ns t ch global clock high time 5 .0 6 .0 10 .0 0 .0 ns t cl global clock low time 5 .0 6 .0 10 .0 0 .0 ns t co1 global clock to output delay 8 .0 9 .0 14 .0 0 .0 ns t cnt global clock minimum clock period c1 = 35 pf 13 .0 15 .0 25 .0 40 .0 ns f cnt maximum internal global clock frequency (6) 76.9 66.6 40 .0 0 .0 mhz t asu array clock input setup time 3.0 4.0 8 .0 40 .0 ns t ah array clock input hold time 6.0 7.0 8 .0 ns t ach array clock high time 6 .0 7.5 12.5 ns t acl array clock low time 6 .0 7.5 12.5 ns t odh output data hold time after clock c1 = 35 pf (7) 1.0 1.0 1.0 ns t aco1 array clock to output delay c1 = 35 pf 16 .0 18 .0 22 .0 40 .0 ns t acnt array clock minimum clock period 13 .0 15 .0 25 .0 40 .0 ns f acnt maximum internal array clock frequency (6) 76.9 66.6 40 .0 mhz www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 775 classic epld f amil y data sheet notes to tables: (1) these values are specified in table 15 on page 770 . (2) see application note 78 (understanding max 5000 & classic timing) in th is data book f or information on internal timing parameters. (3) the non-turbo adder must be added to this parameter when the turbo bit option is off. (4) sample-tested only for an output change of 500 mv. (5) the f max values represent the highest frequency for pipelined data. (6) measured with the device programmed as a 24-bit counter. (7) sample-tested only. this parameter is a guideline based on extensive device characterization and applies for both global and array clocking . table 22. ep910i internal timing parameters symbol parameter condition ep910i-12 ep910i-15 ep910i-25 unit min max min max min max t in input pad and buffer delay 2 .0 3 .0 2 .0 ns t io i/o input pad and buffer delay 0 .0 0 .0 0 .0 ns t lad logic array delay 8 .0 9 .0 17 .0 ns t od output buffer and pad delay c1 = 35 pf 2 .0 3 .0 6 .0 ns t zx output buffer enable delay c1 = 35 pf 5 .0 6 .0 9 .0 ns t xz output buffer disable delay c1 = 5 pf 5 .0 6 .0 9 .0 ns t su register setup time 4 .0 5 .0 5 .0 ns t h register hold time 4 .0 6 .0 11 .0 ns t ic array clock delay 12 .0 12 .0 14 .0 ns t ics global clock delay 4 .0 3 .0 6 .0 ns t fd feedback delay 1 .0 1 .0 3 .0 ns t clr register clear time 11 .0 12 .0 20 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
notes: www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 777 ep1810 epld f e a tures n high-performance, 48-macrocell classic epld C combinatorial speeds with t pd as fast as 20 ns C counter frequencies of up to 50 mhz C pipelined data rates of up to 62.5 mhz n programmable i/o architecture with up to 64 inputs or 48 outputs n programmable clock option for independent clocking of all registers n macrocells individually programmable as d, t, jk, or sr flipflops, or for combinatorial operation n available in the following packages (see figure 15 ) C 68-pin ceramic pin-grid array (pga) C 68-pin plastic j-lead chip carrier (plcc) figure 15. ep1810 pack age pi n- out diagrams package outlines not drawn to scale. see t able 32 on page 785 of this data sheet for pga package pin-out information. windows in ceramic packages only . 68-pin pga l k j h g f e d c b a bottom v iew 1 2 3 4 5 6 7 8 9 10 1 1 ep1810 ep1810 68-pin plcc i/o i/o i/o i/o input input input clk1/input vcc clk2/input input input input input input input i/o i/o i/o i/o i/o input input input clk4/input vcc clk3/input input input input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
778 altera corporation classic epld f amil y data sheet general description altera ep1810 devices offer l si d ensity, ttl-equivalent speed, and low- power consumption. ep1810 devices have 48 macrocells, 16 dedicated input pins, and 48 i/o pins (see figure 16 ). ep1810 devices are divided into four quadrants, each containing 12 macrocells. of the 12 macrocells in each quadrant, 8 have quadrant feedback and are local macrocells (see feedback select on page 749 of this data sheet for more information). the remaining 4 macrocells in the quadrant are global macrocells. both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells. ep1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. if the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 779 classic epld f amil y data sheet figure 16. ep1810 block diagram pin nu mbers a re for j-lead packages. pin nu mbers in p arentheses are for pga packages. ( k 4 ) ( l 4 ) ( k 5 ) ( l 5 ) ( l 6 ) ( k 7 ) ( l 7 ) ( k 8 ) i n p u t i n p u t i n p u t i n p u t / c l k 1 i n p u t / c l k 2 i n p u t i n p u t i n p u t ( b 4 ) 5 6 ( a 5 ) 5 5 ( b 5 ) 5 4 ( a 6 ) 5 3 ( a 7 ) 5 1 ( b 7 ) 5 0 ( a 8 ) 4 9 ( b 8 ) 4 8 i n p u t i n p u t i n p u t i n p u t / c l k 4 i n p u t / c l k 3 i n p u t i n p u t i n p u t q u a d r a n t a ( f 1 ) ( g 2 ) ( g 1 ) ( h 2 ) ( h 1 ) ( j 2 ) ( j 1 ) ( k 1 ) ( k 2 ) ( l 2 ) ( k 3 ) ( l 3 ) l o c a l b u s q u a d r a n t a m a c r o c e l l 4 8 m a c r o c e l l 4 7 m a c r o c e l l 4 6 m a c r o c e l l 4 5 m a c r o c e l l 4 4 m a c r o c e l l 4 3 m a c r o c e l l 4 2 m a c r o c e l l 4 1 m a c r o c e l l 4 0 m a c r o c e l l 3 9 m a c r o c e l l 3 8 m a c r o c e l l 3 7 q u a d r a n t d ( e 1 ) 6 8 ( e 2 ) 6 7 ( d 1 ) 6 6 ( d 2 ) 6 5 ( c 1 ) 6 4 ( c 2 ) 6 3 ( b 1 ) 6 2 ( b 2 ) 6 1 ( a 2 ) 6 0 ( a 3 ) 5 9 ( b 3 ) 5 8 ( a 4 ) 5 7 l o c a l b u s q u a d r a n t d m a c r o c e l l 1 3 m a c r o c e l l 1 4 m a c r o c e l l 1 5 m a c r o c e l l 1 6 m a c r o c e l l 1 7 m a c r o c e l l 1 8 m a c r o c e l l 1 9 m a c r o c e l l 2 0 m a c r o c e l l 2 1 m a c r o c e l l 2 2 m a c r o c e l l 2 3 m a c r o c e l l 2 4 ( l 8 ) ( k 9 ) ( l 9 ) ( l 1 0 ) ( k 1 0 ) ( k 1 1 ) ( j 1 0 ) ( j 1 1 ) ( h 1 0 ) ( h 1 1 ) ( g 1 0 ) ( g 1 1 ) l o c a l b u s q u a d r a n t b m a c r o c e l l 3 6 m a c r o c e l l 3 5 m a c r o c e l l 3 4 m a c r o c e l l 3 3 m a c r o c e l l 3 2 m a c r o c e l l 3 1 m a c r o c e l l 3 0 m a c r o c e l l 2 9 m a c r o c e l l 2 8 m a c r o c e l l 2 7 m a c r o c e l l 2 6 m a c r o c e l l 2 5 ( a 9 ) 4 7 ( b 9 ) 4 6 ( a 1 0 ) 4 5 ( b 1 0 ) 4 4 ( b 1 1 ) 4 3 ( c 1 1 ) 4 2 ( c 1 0 ) 4 1 ( d 1 1 ) 4 0 ( d 1 0 ) 3 9 ( e 1 1 ) 3 8 ( e 1 0 ) 3 7 ( f 1 1 ) 3 6 l o c a l b u s q u a d r a n t c q u a d r a n t b q u a d r a n t c g l o b a l m a c r o c e l l s l o c a l m a c r o c e l l s m a c r o c e l l 1 m a c r o c e l l 2 m a c r o c e l l 3 m a c r o c e l l 4 m a c r o c e l l 5 m a c r o c e l l 6 m a c r o c e l l 7 m a c r o c e l l 8 m a c r o c e l l 9 m a c r o c e l l 1 0 m a c r o c e l l 1 1 m a c r o c e l l 1 2 g l o b a l b u s 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 1 4 1 5 1 6 1 7 1 9 2 0 2 1 2 2 www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
780 altera corporation classic epld f amil y data sheet figure 17 shows the typical supply current (i cc ) versus frequency for ep1810 eplds. figure 17. i cc vs. frequency of ep1810 devices figure 18 shows the output drive characteristics of ep1810 devices. figure 18. output drive characteristics of ep1810 devices 1 0 0 1 0 1 . 0 0 . 1 f r e q u e n c y 1 0 k h z 1 0 0 k h z 1 m h z 1 0 m h z 6 0 m h z v = 5 . 0 v t = 2 5 c t y p i c a l i a c t i v e ( m a ) c c c c a e p 1 8 1 0 drive characteristics may exceed shown curves . v o o u t p u t v o l t a g e ( v ) e p 1 8 1 0 - 2 0 & e p 1 8 1 0 - 2 5 e p l d s 1 2 3 4 5 i o l i o h 2 0 0 1 5 0 1 0 0 5 0 v c c = 5 . 0 v t a = 2 5 c e p 1 8 1 0 - 3 5 & e p 1 8 1 0 - 4 5 e p l d s v o o u t p u t v o l t a g e ( v ) 1 2 3 4 5 i o l i o h 8 0 6 0 4 0 2 0 v c c = 5 . 0 v t a = 2 5 c t y p i c a l i o u t p u t c u r r e n t ( m a ) o t y p i c a l i o u t p u t c u r r e n t ( m a ) o www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 781 classic epld f amil y data sheet operating conditions tables 23 through 27 p rovide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for ep1810 devices . table 23. ep1810 device absolute maximum ratings notes (1) , (2) symbol parameter conditions min max unit v cc supply voltage with respect to ground (3) C2.0 (C0.5) 7.0 v v i dc input voltage with respect to ground (3) C2.0 (C0.5) 7.0 v i max dc v cc or ground current C300 (C400) 300 (400) ma i out dc output current, per pin C25 25 ma t stg storage temperature no bias C65 150 c t amb ambient temperature under bias C6 5 13 5 c t j junction temperature ceramic packages, un der bias 1 50 c plastic packages, under bias 135 c table 24. ep1810 device recommended operating conditions note (2) symbol parameter conditions min max unit v cc supply voltage (4) 4.75 (4.5) 5.25 (5.5) v v i input voltage C 0 .3 v cc + 0.3 v v o output voltage 0 v cc v t a operating temperature for commercial use 0 70 c for industrial use C40 85 c t r input rise time ( 5 ) 50 ns t f input fall time ( 5 ) 50 ns table 25. ep1810 device dc operating conditions notes ( 6 ), ( 7 ) symbol parameter conditions min max unit v ih high-level input voltage 2.0 v cc + 0.3 v v il low-level input voltage C0.3 0.8 v v oh high-level ttl output voltage i oh = C4 ma dc (8) 2.4 v high-level cmos output voltage i oh = C 0.6 ma dc (8) 3.84 v v ol low-level output voltage i ol = 4 ma dc (8) 0.45 v i i i/o pin leakage current of dedicated input pins v i = v cc or ground C10 10 a i oz tri-state output leakage current v o = v cc or ground C10 10 a www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
782 altera corporation classic epld f amil y data sheet n otes to tables: (1) see the operating requirements for altera devices data sheet in th is data book. (2) numbers in parentheses are for industrial-temperature-range devices. (3) the minimum dc input is C0.3 v. during transitions, the inputs may undershoot to C2.0 v or overshoot to 7.0 v for input currents less than 100 ma and periods less than 20 ns. (4) maximum v cc rise time is 50 ms. (5) for ep1810 clocks: t r and t f = 100 ns (50 ns for industrial-temperature-range versions). (6) typical values are for t a = 25 c and v cc = 5 v. (7) these values are specified in table 24 on page 781 . (8) the i oh parameter refers to high-level ttl or cmos output current; the i ol parameter refers to low-level ttl output current. (9) the device ca pacitance is measured at 25 c and is sa mple-tested only. (10) measured with a device programmed as four 12-bit counters. table 26. ep1810 device capacitance note ( 9 ) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 20 pf c io i/o pin capacitance v out = 0 v, f = 1.0 mhz 20 pf c clk 1 c clk1 p in capacitance v in = 0 v, f = 1.0 mhz 25 pf c clk2 c clk2 pin capacitance v in = 0 v, f = 1.0 mhz 160 pf table 27. ep1810 device i cc supply current notes ( 2 ), ( 6 ), ( 7 ) symbol parameter conditions speed grade min typ max unit i cc1 v cc supply current v i = v cc or ground, no load, ( 10 ) -20, -25 50 150 a (non-turbo, standby) -35, -45 35 150 a i cc2 v cc supply current v i = v cc or ground, no load, f = 1.0 mhz ( 10 ) -20, -25 20 40 ma (non-turbo, active) -35, -45 10 30 (40) ma i cc3 v cc supply current (turbo, active) v i = v cc or ground, no load f = 1.0 mhz ( 10 ) -20, -25 180 225 (250) ma -35, -45 100 180 (240) ma www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 783 classic epld f amil y data sheet tables 28 through 31 show the timing parameters for ep1810-20, ep1810- 25, ep1810-35, and e p1810-45 devices. table 28. ep1810-20 & ep1810-25 e xternal timing parameters note (1) symbol parameter conditions ep1810-20 ep1810-25 non-turbo adder unit min max min max ( 2 ) t pd1 input to non-registered output c1 = 35 pf 20 .0 25 .0 25 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 22 .0 28 .0 25 .0 ns t su global clock setup time 13 .0 17 .0 25 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 ns t ch global clock high time 8 .0 10 .0 0 .0 ns t cl global clock low time 8 .0 10 .0 0 .0 ns t co1 global clock to output delay c1 = 35 pf 15 .0 18 .0 0 .0 ns t cnt minimum global clock period (3) 20 .0 25 .0 0 .0 ns f cnt maximum internal frequency (3) 50 .0 40 .0 0 .0 mhz t asu array clock setup time 8 .0 10 .0 25 .0 ns t ah array clock hold time 8 .0 10 .0 0 .0 ns t aco1 array clock to output delay c1 = 35 pf 20 .0 25 .0 25 .0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 0.0 ns t acnt array clock maximum clock period (3) 20 .0 25 .0 0 .0 ns f acnt maximum internal array clock frequency (3) 50 .0 40 .0 0 .0 ns f max maximum clock frequency (5) 62.5 50 .0 0 .0 mhz table 29. ep1810-20 and ep1810-25 in ternal timing parameters symbol parameter conditions ep1810-20 ep1810-25 non-turbo adder unit min max min max ( 2 ) t in input pad and buffer delay 5 .0 7 .0 0 .0 ns t io i/o input pad and buffer delay 2 .0 3 .0 0 .0 ns t lad logic array delay 9 .0 12 .0 25 .0 ns t od output buffer and pad delay c1 = 35 pf 6 .0 6 .0 0 .0 ns t zx output buffer enable delay c1 = 35 pf 6 .0 6 .0 0 .0 ns t xz output buffer disable delay c1 = 5 pf (6) 6 .0 6 .0 0 .0 ns t su register setup time 8 .0 10 .0 0 .0 ns t h register hold time 5 .0 10 .0 0 .0 ns t ic array clock delay 9 .0 12 .0 25 .0 ns t ics global clock delay 4 .0 5 .0 0 .0 ns t fd feedback delay 3 .0 3 .0 C25 .0 ns t clr register clear time 9 .0 12 .0 25 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
784 altera corporation classic epld f amil y data sheet table 30. ep1810-35 & ep1810-45 external timing parameters note (1) symbol parameter conditions ep1810-35 ep1810-45 non-turbo adder unit min max min max ( 2 ) t pd1 input to non-registered output c1 = 35 pf 35 .0 45 .0 30 .0 ns t pd2 i/o input to non-registered output c1 = 35 pf 40 .0 50 .0 30 .0 ns t su global clock setup time 25 .0 30 .0 30 .0 ns t h global clock hold time 0 .0 0 .0 0 .0 ns t ch global clock high time 12 .0 15 .0 0 .0 ns t cl global clock low time 12 .0 15 .0 0 .0 ns t co1 global clock to output delay c1 = 35 pf 20 .0 25 .0 0 .0 ns t cnt minimum global clock period (3) 35 .0 45 .0 0 .0 ns f cnt maximum internal frequency (3) 28.6 22.2 0 .0 mhz t asu array clock setup time 10 .0 11 .0 30 .0 ns t ah array clock hold time 15 .0 18 .0 0 .0 ns t aco1 array clock to output delay c1 = 35 pf 35 .0 45 .0 30 .0 ns t odh output data hold time after clock c1 = 35 pf (4) 1.0 1.0 ns t acnt array clock maximum clock period (3) 35 .0 45 .0 0 .0 ns f acnt maximum internal array clock frequency (3) 28.6 22.2 0 .0 ns f max maximum clock frequency (5) 40 33.3 0 .0 mhz table 31. ep1810-35 & ep1810-45 internal timing parameters symbol parameter conditions ep1810-35 ep1810-45 non-turbo adder unit min max min max ( 2 ) t in input pad and buffer delay 7 .0 6 .0 0 .0 ns t io i/o input pad and buffer delay 5 .0 5 .0 0 .0 ns t lad logic array delay 19 .0 28 .0 30 .0 ns t od output buffer and pad delay c1 = 35 pf 9 .0 11 .0 0 .0 ns t zx output buffer enable delay c1 = 35 pf 9 .0 11 .0 0 .0 ns t xz output buffer disable delay c1 = 5 pf (6) 9 .0 11 .0 0 .0 ns t su register setup time 10 .0 10 .0 0 .0 ns t h register hold time 15 .0 18 .0 0 .0 ns t ic array clock delay 19 .0 28 .0 30 .0 ns t ics global clock delay 4 .0 8 .0 0 .0 ns t fd feedback delay 6 .0 7 .0 C30 .0 ns t clr register clear time 24 .0 32 .0 30 .0 ns www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
altera corporation 785 classic epld f amil y data sheet notes to tables: (1) these values are specified in table 24 on page 781 . (2) the non-turbo adder must be added to this parameter when the turbo bit option is off. (3) measured with a device programmed as four 12-bit counters. (4) sample-tested only. this parameter is a guideline based on extensive device characterization. this parameter applies for both global and array clocking. (5) the f max values represent the highest frequency for pipelined data. (6) sample-tested only for an output change of 500 mv. pin-out information table 32 p rovides pin-out information for ep1810 devices in 68-pin pga packages. table 32. ep1810 p ga pin-outs pin function pin function pin function pin function a2 i/o b9 i/o f10 gnd k4 input a3 i/o b10 i/o f11 i/o k5 input a4 i/o b11 i/o g1 i/o k6 vcc a5 input c1 i/o g2 i/o k7 input a6 clk4 /input c2 i/o g10 i/o k8 input a7 clk3 /input c10 i/o g11 i/o k9 i/o a8 input c11 i/o h1 i/o k10 i/o a9 i/o d1 i/o h2 i/o k11 i/o a10 i/o d2 i/o h10 i/o l2 i/o b1 i/o d10 i/o h11 i/o l3 i/o b2 i/o d11 i/o j1 i/o l4 input b3 i/o e1 i/o j2 i/o l5 clk1 /input b4 input e2 i/o j10 i/o l6 clk2 /input b5 input e10 i/o j11 i/o l7 input b6 vcc e11 i/o k1 i/o l8 i/o b7 input f1 i/o k2 i/o l9 i/o b8 input f2 gnd k3 i/o l10 i/o www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet
copyright ? 1995, 1996, 1997, 1998 , 1 9 9 9 altera corporation, 101 innovation drive, san jose, c a 95134, usa, all rights r eserved. by accessing this information, you ag r ee to be bound by the terms of alteras legal notice. www.datasheet www.datasheet www.datasheet www.datasheet 4u 4u4u 4u .com .com .com .com 4 .com u datasheet

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